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hcom's avatar
hcom
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Signal Tap example from Intel training course always fails timing

I am using Quartus Prime 21.1.0 Build 169 03/24/2021 SC Pro Edition to target a Cyclone 10 GX (10CX085) FPGA. I followed this Intel training course to set up Signal Tap: https://learning.intel.co...
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
4 years ago

Hi hcom,

Any further update? Have you pass the timing constraints with the SDC constraints provided?

Best regards,
Sheng


hcom's avatar
hcom
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

@ShengN_Intel No, there is no solution yet. It still fails timing.

I still need a solution, but nothing I have tried has worked.

  • ShengN_altera's avatar
    ShengN_altera
    Icon for Super Contributor rankSuper Contributor
    4 years ago

    Hi @hcom ,

    I think you can straight set false path from those two fail timing nodes. Try to modify a bit the original Quartus SDC template like below.

    proc set_s10_false_path_constraint { } { if {$::TimeQuestInfo(family) == "Cyclone 10 GX"}

    { set_false_path -from "the node"

    set_false_path -from "the node" } }

    Best regards,
    Sheng