Signal Tap example from Intel training course always fails timing

Hi hcom,

I found something from Cyclone 10 GX datasheet about jtag timing parameters below.

https://www.marutsu.co.jp/contents/shop/marutsu/ds/c10gx-51002.pdf

May be you can try the SDC constraints with these parameters:

create_clock -name altera_reserved_tck -period 30 [get_ports altera_reserved_tck]

#cut all paths to and from altera_reserved_tck
set_clock_groups -asynchronous -group [get_clocks altera_reserved_tck]

# I/O min delays
set_input_delay -clock altera_reserved_tck [get_ports altera_reserved_tdi] -min 5 #(hold constraints)
set_input_delay -clock altera_reserved_tck [get_ports altera_reserved_tms] -min 5 #(hold constraints)
set_output_delay -clock altera_reserved_tck -clock_fall [get_ports altera_reserved_tdo] -min 11 #(constraints tjpco at falling edge)

# I/O max delays
set_input_delay -clock altera_reserved_tck [get_ports altera_reserved_tdi] -max 28 #(setup constraints: tck - tdi)
set_input_delay -clock altera_reserved_tck [get_ports altera_reserved_tms] -max 27 #(setup constraints: tck - tms)
set_output_delay -clock altera_reserved_tck -clock_fall [get_ports altera_reserved_tdo] -max 30

Best regards,
Sheng