Signal Tap example from Intel training course always fails timing

Hi hcom,

Intel training course did mention the template in Timing Analyzer Cookbook as well, linked here.

I believe the JTAG signal constraints template in Cookbook can be used and function well. Just the method is different which used fitter-specific constraints.

Most likely the timing failure is because of the ports {altera_reserved_tdo}. Timing fails there.

I also found something here (page 25) regarding SDC command:

set_max_delay - To relax timing analysis for the setup/ hold checks to not fail.

set_false_path - Identifies specific timing paths as being false. This constraint removes timing requirements on these false paths so that they are not considered during the timing analysis.

I think you can add the second suggestion in top post into text editor template or use this one:

--- Quote Start ---

set jtag_33Mhz_t_period 30

create_clock -name {altera_reserved_tck} -period $jtag_33Mhz_t_period [get_ports {altera_reserved_tck}]

set_clock_groups -asynchronous -group {altera_reserved_tck}

set_max_delay -to [get_ports { altera_reserved_tdo } ] 0

--- Quote End ---

Both methods should work properly as well. The periods 10Mhz or 33Mhz should be both okay depend on which one you choose.

Hope it helps.

Best regards,
Sheng

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.