Signal Spy vs Force in Modelsim

Use Signal Spy in mixed language or VHDL designs where you want to hierarchically control elements in a VHDL block. In pure Verilog designs, this is not required, because Force already allows hierarchical references.

Pete

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Perhaps a better question would be where would I use signal spy and where would I be better of trying to force signals?

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A better method is to create a testbench that models the inputs and checks the outputs for the entity being tested. Then you don't need to force signals at all, nor do you necessarily need to bring out internal signals for monitoring since you can have assertion checking that the top level outputs are producing the correct results. Lower level blocks are tested with their own testbench to verify correct operation. My $0.02

Kevin Jennings

Thank you for the responses. THe biggest reason I have for trying to use something other than a test bench is that I need to check what happens when obscure conditions exist. Getting my design into those situations would be difficult with a test bench so I though that perhaps this was the best way to do it.

Thank you

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Thank you for the responses. THe biggest reason I have for trying to use something other than a test bench is that I need to check what happens when obscure conditions exist. Getting my design into those situations would be difficult with a test bench so I though that perhaps this was the best way to do it.

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Testbenches are supposed to try to cover all conditions, obscure or not. One tremendous benefit is that once you have the testbench and all your checking completed the first time, you can then reuse that to validate that any changes to your design still correctly handle all conditions. Using 'force' statements doesn't really give you that guarantee. Again, my $0.02

Kevin Jennings