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Altera_Forum's avatar
Altera_Forum
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14 years ago

Signal Spy vs Force in Modelsim

What are the benifits using signal spy as opposed to trying to "Force" certain signals to do things in the designs. Perhaps a better question would be where would I use signal spy and where w...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Use Signal Spy in mixed language or VHDL designs where you want to hierarchically control elements in a VHDL block. In pure Verilog designs, this is not required, because Force already allows hierarchical references.

Pete