Signal not assigned in init state

PuqmaStar,

It just bothered me that I could not see what was wrong so I took a few minutes and ran it myself. Seems to work fine for me. I had to add

LIBRARY IEEE; 

at the top of your code to get it to compile and changed count to 5 instead of 100. Perhaps you just missed that in the cut ans paste. Then did a simple test bench:

-- 
-- Simulation tool : ModelSim-Altera (VHDL)
-- 
LIBRARY ieee;                                               
USE ieee.std_logic_1164.all;    
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
USE std.textio.all;                          
USE ieee.std_logic_textio.all;  
                        
ENTITY TB IS
END TB;
ARCHITECTURE test_arch OF TB IS
	
	
	constant clock_period  : time := 10 ns;
	signal clk             : std_logic := '0';
	
	signal clock_running   : std_logic := '0';
	signal sim_done        : std_logic := '0';
	signal button : std_logic_vector(5 downto 1) := (others => '0');
	signal key    : std_logic_vector(31 downto 0) := (others => '0');
	
	
	component buttonToKey 
		port (
		    clk_50 : in std_logic;
			button : in std_logic_vector(5 downto 1);
			key: out std_logic_vector(31 downto 0)
			);
	end component;
begin
	
	DUT : buttonToKey
		port map (
		    clk_50 => clk,
			button => button,
			key    => key
			);
	/*
		Clock process
	*/
			
	clock_proc : process
	begin
		if(clock_running = '1') then
			wait for clock_period / 2;
			clk <= not clk;
		elsif(sim_done = '1') then
			wait;
		else 
			wait for 20 ns;
		end if;
	end process;
	/*
		Test proc
	*/
	test_proc : process
	begin
--		printf("Test proc\n");
--		printf("clock_period  = %e\n", clock_period);
	
		clock_running <= '1';
	
		wait for 20 * clock_period;
		for i in 1 to 4 loop
			button <= "10000";
			for j in 1 to 25 loop
				wait for 10 * clock_period;
     			end loop;
			button <= "00001";
			wait for 2 * clock_period;
		end loop;
		clock_running <= '0';
	
		sim_done <= '1';
--		printf("done\n");
		wait;
	end process;
			
	
END test_arch;

and DO file to run it:

transcript file ""
transcript file transcript.log
transcript on
if {} {
	vdel -lib rtl_work -all
}
vlib rtl_work
vmap work rtl_work
vcom -2008 -work work {ButtonToKey.vhd}
vcom -2008 -work work {button_test.vht}
vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L fiftyfivenm -L rtl_work -L work -voptargs="+acc"  TB
# add wave *
add wave "/TB/CLK"
add wave "/TB/BUTTON"
add wave -hex "/TB/KEY"
add wave -unsigned "/TB/DUT/count"
add wave -decimal "/TB/DUT/index"
add wave "/TB/DUT/state"
# set sim_time 
# puts $sim_time
set t0 
run -all
set dt  - $t0]
puts $dt
wave zoom full
#  set PrefMain(Editor) {C:/Windows/System32/notepad.exe}
#  edit transcript

and it works just fine:

https://www.alteraforum.com/forum/attachment.php?attachmentid=13409

Note the lines in the DO file that add internal signals to the waveform as Tricky suggested.

You must be doing something wrong in the way you run the simulation. In any event, now that I know I'm not crazy (regardless of what others think) my interest in the problem is over. Suffice it to say there are all sorts of issues with your code, but since it sounds like a school project you should figure it out yourself. Good luck.