Signal not assigned in init state

One way it works if a synchronous reset is implemented. If that is done the state machine starts in init as it should have done. This was not my doing btw. Credit goes to my TA who found that out.

Below the working code:

    if rising_edge( clk_50 ) then
            if rst = '0' then
                state <= init;
            else 
                if state = init AND count = 100 then                                                -- init and assign default char
                    state <= assign;
                    key_int( 3 ) <= x"61";                                                                 -- ASCII 'a'
                    key_int( 2 ) <= x"61"; 
                    key_int( 1 ) <= x"61";
                    key_int( 0 ) <= x"61";
                    count <= ( others => '0' );
    --                key <= "11111111111111111111111111111111";  -- debug
                    
                elsif state = evaluate then                                                            -- check which button is pressed
                    if button = "10000" then                                                            -- button 5: increment ASCII character 
                        state <= assign;
                        count <= ( others => '0' );
                        if unsigned( key_int( index ) ) = x"7A" then                                -- run circular between ASCII char 'a' and 'z'
                            key_int( index ) <= x"61";
                        else
                            key_int( index ) <= key_int( index ) + 1;
                        end if;
                    elsif button = "00001" then                                                        -- button 1: move to next position (start with 1)
                        state <= evaluate;
                        if index = 3 then
                            index <= 0;                                                                        -- overflow protection
                        else
                            index <= index + 1;
                        end if;
                    else
                        state <= evaluate;
                    end if;
                    
                elsif state = assign AND count = 100 then                                            --  assign any changed keys to output                                             
                    count <= ( others => '0' );
                    state <= evaluate;
    --                key <= key_int4 & key_int3 & key_int2 & key_int1;
                    key <= key_int( 3 ) & key_int( 2 ) & key_int( 1 ) & key_int( 0 );
    --                key <= "00000000001111111111000000000011";    -- debug
                else
                    count <= count + 1;
                end if;
            end if;

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It's not related to your question and just my two cents, but this is not a usual way to structure a FSM. Most people would use a case statement for each state. I'm not sure the tools will even recognize your code as a FSM (should still work though).

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Yes you are right. This is not the standard state machine and if I look at the state machine template from the altera website - link (http://quartushelp.altera.com/15.0/mergedprojects/hdl/vhdl/vhdl_pro_state_machines.htm) or here - link (https://www.altera.com/support/support-resources/design-examples/design-software/vhdl/vhd-state-machine.html) it uses case state ..when=> structure but it does not say it is a nessecity.

In the quartus ii handbook volume 1 - link (https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&uact=8&sqi=2&ved=0ahukewjelyg5yu_sahujpiykhc1xd40qfggamaa&url=https%3a%2f%2fwww.altera.com%2fen_us%2fpdfs%2fliterature%2fhb%2fqts%2fqts-qps-5v1.pdf&usg=afqjcngnr1gq2_khvwqn9afvdjhqkzw35g&sig2=k1pkspsuefhkqwmvfcrmxq&bvm=bv.150729734,d.ewe) on page 12-50 it only says that to be recognized as a state machine I must use state type like this

TYPE Tstate IS (state_0, state_1, state_2, state_3, state_4);
 SIGNAL state: Tstate;

and also gives a few more suggestions.

Maybe that explains the strange behaviour? Maybe the case state ..when=> structure or a reset are necessary? Well, I don't know for sure now but since I got it working with above code I am satisfied for now!

Thanks @tricky and @corestar for your help and suggestions!