Signal not assigned in init state

It does look like you should see "key" change. It's not related to your question and just my two cents, but this is not a usual way to structure a FSM. Most people would use a case statement for each state. I'm not sure the tools will even recognize your code as a FSM (should still work though).

It's not clear what you mean by "I already placed a counter in both states so I don't get a timing problem." but the code would be much more clear if you put the counter in a separate process so that it is incremented and reset in one place instead of several.

counter_expired <= '1' when counter = 100 else '0';
counter_proc : process
	begin
		wait until CLK'EVENT and CLK = '1';
		
		if(counter = 100 or reset_counter = '1') then
			counter <= (others => '0');
		else
			counter <= counter + 1;
		end if;
end process counter_proc;

then in the FSM:

   case state is
   when init =>
       if(counter_expired = '1') then
       ...
       end if;
...

If you are using VHDL 2008, you can access internal signal names in a testbench using the VHDL 2008 external names. Some examples here:

http://stackoverflow.com/questions/17287129/vhdl-alias-syntax (http://stackoverflow.com/questions/17287129/vhdl-alias-syntax)

In fact, a simulation is sort of useless if you do not do so. Being VHDL, it is ten times more verbose than necessary, but it works.

Sorry for the unsought for suggestions; clearly had too much time on my hands today.