signal_force in gate-level simulation

Hi Rysc,

Thanks very much for your suggestion, I understand your point. The problem is that my design takes up nearly 90% of the available SRAM and 80% of the logic cells, hence, a big design.

Also, my bug is very suptle, not a catastrophic one. In order for me to spot the problem, I need to acquire quite a lot of data onto a PC via USB. Only after performing some statistical tests in MATLAB is that the problem can be seen. When I run the RTL (or gate-level for that matter), I use textio to write the results into texts files, then I use MATLAB to process the output to check if the error is present. So far, in RTL, I could not reproduce the error.

In conclusion, my error is only indentified after approximately 100ms of run/simulation time, and the output data is quite significant. By looking at the waveforms of signal tap, not possible to spot the problem, not enough data.

I hope the problem is static bug, that could be spot by the gate-level simulation. If not, I would be really in trouble to reproduce the bug and eventually correct it.

To do a gate-level simulation, probably I will need to go over the gate netlist and spot all the required registers manually. This is a huge amount of work. Any other suggestion?

Cheers!