Signal declaration and use

Writing a direct translation of the matlab into VHDL is a terrible idea. It will run slower than matlab (in simulation) and it will not synthesise. Simulation does NOT do anything for your parrallisation - that comes through synthesis. The only way to get there is to architect your circuit on paper before moving to VHDL. VHDL is a description language - if you dont know what you're describing, it will never work.