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Altera_Forum's avatar
Altera_Forum
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14 years ago

Show non input/output node in simulation

Hi!

I'm using Quartus II 9.1 for the in-built simulator, which I learnt to use a while ago.

I'm simulating a project which I designed exclusively in schematics and predefined Mega-Wizard Plugin blocks.

Now, I've always wondered why when I add a non top-level input/output node (i.e. a wire with a label, in the top-level entity or inside another one) to a Vector Waveform File, the node disappears from it after the simulation is done.

how can i see the state of any node in the simulation? [Quartus V9.1]

I know the answer to my problem might be kind of obvious to you guys, but I'm a newbie here ;)

Thanks in advance! ;)

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    The internal Quartus simulator is providing a kind of gate level simulation in the default timing simulation mode. As a consequence, you can only access circuit nodes, that are actually present in the mapped design.

    My rule of thumb, also valid in SignalTap analysis, says, you can tap a signal most likely at it's source, the register or logic element that is actually generating it. If it's sourced at a lower hierarchy level, or e.g. a library component, go there.