Show non input/output node in simulation

The internal Quartus simulator is providing a kind of gate level simulation in the default timing simulation mode. As a consequence, you can only access circuit nodes, that are actually present in the mapped design.

My rule of thumb, also valid in SignalTap analysis, says, you can tap a signal most likely at it's source, the register or logic element that is actually generating it. If it's sourced at a lower hierarchy level, or e.g. a library component, go there.