Should Quartus 18.1 support FF creation by this: Q <= D when rising_edge(CLK); The D and CLK are input ports on a module, and Q is a output port. The Quartus 18.1 breaks with internal error due to this construction.

@sstrell​

While it is not officially supported (I cant find it in any coding guidelines) it has been supported by many tools for many years.

In VHDL, one liners like this actually infer a process sensitive to all signals on the RHS. So

q <= d when rising_edge(clk);

is functionally identical to

process(clk, d)  -- D not needed, but it is needed for full equivolence to one liner.
begin
  if rising_edge(clk) then
    q <= d;
  end if;
end process;