Forum Discussion
MoZdk
Occasional Contributor
Occasional ContributorShould Quartus 18.1 support FF creation by this: Q <= D when rising_edge(CLK); The D and CLK are input ports on a module, and Q is a output port. The Quartus 18.1 breaks with internal error due to this construction.
sstrell
Super Contributor
Super ContributorThat's not standard synthesizable Verilog or VHDL, so of course it will not work.
