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MoZdk's avatar
MoZdk
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Should Quartus 18.1 support FF creation by this: Q <= D when rising_edge(CLK); The D and CLK are input ports on a module, and Q is a output port. The Quartus 18.1 breaks with internal error due to this construction.

sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
7 years ago

That's not standard synthesizable Verilog or VHDL, so of course it will not work.