Shift register problem

I'm having trouble using the lpm shift register. I want to create a shift register using the lpm shift register in quartus. The problem I think is that I'm trying to use it on a clocked environment while the megafunction is not clocked. It compiles fine but my signals are synthesized away for some reason and I need them for the code to work. Here is my code:

library ieee;
use ieee.std_logic_1164.all;
entity shift_register_2 is
	port
	(
		clk,reset: in std_logic;
		w: in std_logic;
		z: out std_logic
	);
end shift_register_2;
architecture structure of shift_register_2 is
	signal r_in: std_logic_vector(3 downto 0);
	signal r_out: std_logic_vector(3 downto 0);
	
	component shift
	port
	(
		data		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
		distance		: IN STD_LOGIC ;
		result		: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
	);
	end component;
	
begin
	process(clk,reset,w)
	begin
		if(reset='1') then
			r_in <= "0000";
		elsif(clk'event and clk='1') then
			r_in <= w & r_out(2 downto 0);
		end if;
	end process;
	
	process(r_out)
	begin
		if(r_out="1001" OR r_out="1111") THEN
			z<='1';
		else z<='0';
		end if;
	end process;
	
	stage0: shift port map(r_in,'1',r_out);
end structure;