Altera_Forum
Honored Contributor
Honored ContributorShift Register: different behaviour between QII 8.0 and 10.1
I have created the following shift register using Quartus II 8.0:
entity shiftreg is generic ( data_size : integer := 8 ); port ( clk : in std_logic; clr : in std_logic; data_in : in std_logic; data_out : out std_logic_vector (data_size - 1 downto 0) ); end shiftreg; architecture shiftreg of shiftreg is signal data_wire : std_logic_vector (data_size - 1 downto 0); begin process (clk, clr, data_in, data_wire) variable count_data : integer; begin if (clr = '1') then data_wire <= (others =>'0'); else if (clk'event and clk = '1') then data_wire(data_size - 1 downto 1) <= data_wire(data_size - 2 downto 0); data_wire(0) <= data_in; end if; end if; end process; data_out <= data_wire; end shiftreg; Performed the simulation using Altera-ModelSIM 6.6c and obtained the "correct" results as shown in Fig. 1. After creating a new project and compile it using Quartus II 10.1, I have performed a new simulation (same stimuli) and obtained the "incorrect" behaviour as shown in Fig. 2. Used Timequest to guide the placement and verified with the Technology Map Viewer (post-fiiting) that the resource usage and netlist are indeed the same in both version of Quartus (clearly the device used was also consistent EP1C12Q240C7). Is this a problem related with the simuation tool and its libraries? what is that I am missing? Thanks in advance for any reply
