shift register coding problem

Hi,

I wonder if someboy could take a look on my code on 5x9 shift register. It seems to me that input d is connected to the design. I am using multidimensional array.

I am new to VHDL :confused:

library ieee ;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity ShiftReg is

port( d: IN STD_LOGIC_VECTOR(4 downto 0);

Q: OUT STD_LOGIC_VECTOR(4 downto 0);

Clk: IN STD_LOGIC

);

end ShiftReg;

architecture archi of ShiftReg is

type register5x9 is array (0 to 4) of STD_LOGIC_VECTOR (8 downto 0);

signal tmp: register5x9;

begin

process (Clk)

begin

if Clk'event and Clk='1' then

tmp(0)(8) <= d(0);

tmp(1)(8) <= d(1);

tmp(2)(8) <= d(2);

tmp(3)(8) <= d(3);

tmp(4)(8) <= d(4);

for i in 8 downto 1 loop

for j in 4 downto 1 loop

tmp(j-1)(i-1) <= tmp(j)(i);

end loop;

end loop;

end if;

Q(0) <= tmp(0)(0);

Q(1) <= tmp(1)(0);

Q(2) <= tmp(2)(0);

Q(3) <= tmp(3)(0);

Q(4) <= tmp(4)(0);

end process;

end archi;