Honored ContributorHi everyone!
I' am writing a project where both program for nios and component implemented with VHDL need to access SDRAM on DE2 board. I am using Qsys. So, How it can be implemented? Is it possible at all? If yes, what kind of components in Qsys configuration can make this SDRAM shared . Need your advice. Thank you.
Honored ContributorThe Avalon-MM bus is designed for multi-master operation, so what you want is:
* NIOS II processor (Avalon-MM master) * Your logic that would like to access the SDRAM (Avalon-MM master) * SDRAM controller (Avalon-MM slave) Basically, as long as you implement your logic with an Avalon-MM master interface, it can share the SDRAM. Your logic might also have an Avalon-MM slave interface, eg., if the NIOS processor was going to access control registers to enable or check the status of your logic. Cheers, DaveHonored ContributorThanks, Dave.
I try using Avalon-MM Pipeline Bridge. Will see if it works. Regards, Lyubov
