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Altera_Forum's avatar
Altera_Forum
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13 years ago

shared SDRAM on DE2

Hi everyone! I' am writing a project where both program for nios and component implemented with VHDL need to access SDRAM on DE2 board. I am using Qsys. So, How it can be implemented? Is ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

The Avalon-MM bus is designed for multi-master operation, so what you want is:

* NIOS II processor (Avalon-MM master)

* Your logic that would like to access the SDRAM (Avalon-MM master)

* SDRAM controller (Avalon-MM slave)

Basically, as long as you implement your logic with an Avalon-MM master interface, it can share the SDRAM.

Your logic might also have an Avalon-MM slave interface, eg., if the NIOS processor was going to access control registers to enable or check the status of your logic.

Cheers,

Dave