SGDMA Write Master FIFO

You are correct, streaming data should only enter the write master when ready and valid are both high. The used signal may roll over to 0x0 because anywhere in the logic that requires the "true" fill level the fifo_full bit is also used. So when you see used signal go from 0xF to 0x0 the fifo_full signal should be high (so the true used is 0x10). When you see the used signal go from 0x0 to 0xF you are seeing the "true" used go from 0x10 to 0x0F.

I recommend setting up a trigger for the ST interface and making sure your logic isn't inserting zeros and then stopping due to the FIFO filling up. I just checked and the write master out of reset will assert the ready signal so if your component has valid asserted it'll start shoveling data into the FIFO.