SGDMA Write Master FIFO

Hi,

I'm using the modular SGDMA which I was pointed to by BadOmen in the thread that I linked to at the beginning of this thread.

I'm signal tapping the FIFO of the write master because I think I tracked the problem down to this very spot. The results I get from my tests pointed me to this FIFO because if I set up this FIFO in the SOPC builder to a depth of 32 then the same "error" happens except that the first 32 SGDMA transfers contain "old" data (-> data that was already in the FIFO before the current transfer started). So in my opinion there is a straight relationship between this FIFO and my problem.

I also don't think that my ADC module is delivering data to the SGDMA Write master before the transfer started because if I understand the Avalon streaming interface specification correctly, data is only "flowing" from the source (my ADC module) to the sink (SGDMA Write Master) if both streaming signals "ready" and "valid" are asserted. This is also to be seen in the signal tap screenshot.

In fact, the "valid" signal in my ADC streaming interface is just mirroring the "ready" signal of the write master because my module is constantly ready to provide current data.

The next thing that I wonder about is the fact that the "usedw" signals of the write master FIFO jump from 0x0 to 0xF and back to 0x0 without any intermediate states (see attachment).

If it's necessary to provide additional signal tap recordings I would provide them. Please tell me what signals may be of interest.

Finally, I could live with this effect. I just would like to know if I made an error during the system building process or if it's just the way it's intended to be.

Regards,

Maik