setup timing from fifo

For fifo, there are some constrain mention in the user guide: https://www.intel.com/programmable/technical-pdfs/683522.pdf, You may take a look if it suite your case

When you set a false path, this means that you do not care whether that path meet any timing wrt to clock. My suggestion is to send us your whole design.qar to take a look first. My suggestion is to use set_multicycle path is the path is too long, or add register in btw the path.