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evyatar
New Contributor
New Contributorsetup timing from fifo
a strange setup timing violation: the path is from the 'write enable' of a FIFO, to another register in the design. it seems like a problem in the Quartus 2 (64 bit V14.1.0 B186 12/3/14 SJ Full Ver...
evyatarNew Contributor
New ContributorI will check this, thank you.
but let say there are too many clock in the design. is this falling path really problematic? please note that it start from the FIFO WE, and continue towards another block trough the FIFO data out port. it seems that this path should be constrained as false path.
what do you think?
