Setting up Generated Clock Constraints for PLL in NIOS

My design is based on a Nios Processor in an Cyclone 3 FPGA.

I am working with the Quartus TimeQuest Timing Analyzer and trying to Create a Generated Clock constraint for a PLL that we have in the Nios Processor. I am using the GUI of TimeQuest for this.

In the Create Generated Clock GUI window I can set the clock name and the source... but I do not know what should I put in the "target" box in the Create Generated Clock window?

My pll is called altpll_0_c0. So I know that the target should somehow refer to this PLL... from the "name finde window" I get the all names that contain "altpll_0_c0"... there are two that I think that could be the target clock, but one says:

inst\|cycloneIII_embedded_evaluation_kit_standard_sopc_reset_altpll_0_c0_out_domain_synch\|data_in_d1|clk

and the other

inst\|cycloneIII_embedded_evaluation_kit_standard_sopc_reset_altpll_0_c0_out_domain_synch\|data_out\|clk

I do not know which one to choose... one contains "data_in_d1" and the other "data_out"

I am confused... Any comments/help is welcome