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Altera_Forum
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13 years ago

Setting timing constraints

I'm very new to timing analysis (actually just 1 day into it). Have taken the online TimeQuest course. I have successfully set the timing constraints for my clocks. Now I need to set the timing constraints for the various logic registers and paths within my design. I can't find ANY examples or help to show me how to do that as a beginner. They show you a lot about clocks and IO ports, but what about the other internal stuff that needs constraints?

Or am I missing something basic? I don't have any particular timing requirement for getting signals through the logic and out to my output ports. But the internal registers and combinations have to work with the necessary set up times. TimeQuest is showing me where I'm not meeting my requirements, but how do I define what those requirements are and how can I fix it?

Appreciate any pointers to where I can learn about that.

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    To get the right timing constraints for internal registers and paths all you have to do is make sure you have properly specified the clock inputs to your design in the SDC file. Quartus and TimeQuest will take care of the rest because the software already knows everything about what goes on internally. The only extra constraints you might need or want to add are multi-cycle constraints that help loosen the timing specifications where this can be done.

    I highly recommend this document by rysc from the Altera Wiki:

    http://www.alterawiki.com/wiki/file:timequest_user_guide.pdf (http://www.alterawiki.com/wiki/file:timequest_user_guide.pdf)

    It is by far the best TimeQuest guide out there.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Thanks. So since I have already done that and the results after the fitter is run are showing me that some things do not meet timing, that means that I have to make some changes to the design, perhaps delay a clock by a cycle, to meet the timing. Its not able to do it automatically.

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    The fitter tries to get timing closure by changing placement and adjusting path lengths but it can't always get there. One of the things to consider when trying to get timing closure is that by improving timing on non-failing paths you can sometimes get closure on the failing paths. This is because the fitter can then put a higher priority on the failing paths without having to worry about the other paths. Identifying multi-cycle paths and entering them in the SDC file is one of the easiest ways to help get to closure. Another thing to do is use the timing optimization adviser in Quartus. It will guide you through which fitter assignments are best suited to timing critical designs. This is the first thing I always do.

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I saw something about the timing optimizer adviser in the training or tutorial. But now I can't find it. I am using the free web edition, not the subscription version. Is it something that is not in my version? Can you let me know where to find the adviser?

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Tools -> Advisors -> Timing Optimization Advisor. It's really just the the settings already available under Assignments -> Settings, but organized to show the ones that help timing most of the time.

    The big ones are having synthesis optimize for Speed and have Physical Synthesis on. That's 90% of the gain.

    Go into TimeQuest and do Report Setup Summary(I assume it's a setup failure). Right click on the worst domain, Report Timing. Change the detail to Full Path and number of paths to 100. Then sit and look at the worst path that comes up. What's the setup relationship? Does that seem right? (It's based on the clocks you described). What about the clock skew? Is that correct? (If it's pretty small, say under +/300ps, then your clock is on a global. You can probably do report_timing with the -detail set to path_only, which just hides some of the clock details into a single number. THe slack is still the same). Finally, look at the data path under the Path tab(part of the Data Arrival). Try to figure out how that correlates to your logic, why it's so long, etc. By far, the best thing to do is to change your code to make the path smaller, but it's also one of the more difficult things to do and not always possible.