To get the right timing constraints for internal registers and paths all you have to do is make sure you have properly specified the clock inputs to your design in the SDC file. Quartus and TimeQuest will take care of the rest because the software already knows everything about what goes on internally. The only extra constraints you might need or want to add are multi-cycle constraints that help loosen the timing specifications where this can be done.
I highly recommend this document by rysc from the Altera Wiki:
http://www.alterawiki.com/wiki/file:timequest_user_guide.pdf (
http://www.alterawiki.com/wiki/file:timequest_user_guide.pdf)
It is by far the best TimeQuest guide out there.