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Altera_Forum's avatar
Altera_Forum
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17 years ago

Setting output value in waveform file...

Hi,

I have a waveform file with some input and outputs....

When I simulate, I get what it's expected... So, there's no problem.

But, I would to set some output (at the begining of the waveform) to simulate a previous state... in the waveform I can set the outputs from XXXX state to a defined state... But, of course, when I launch the simulation, the outputs don't stay a these values ?

I tried to change the output pins to bidir pins, (in the .bdf and the .wvf) but there was no effect...

How can I do ?

Thanks

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    If you are using VHDL, just for simulation, try this:

    signal rx: std_logic_vector(7 downto 0):= "xxxxxxxx"; --Any value

    ----

    ----

    your_output<=rx;

    ------

    rx should be a register output.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Thank you for your reply !

    But I'an using a Vector Waveform File...

    Do you know if it's possible in this case ?

    Thank you.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    I think quartus doesn't allow it, it wouldn't be consistent with the behavior of the hardware.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    I'm not sure, if I'm yet aware of all Quartus simulator features. But I think, it doesn't allow easy forcing of signals during simulation run. This is a privilege of full-featured simulators as ModelSim. But there are most likely means to achieve the intended behaviour anyway. To manipulate an output signal at a given simulation time, you can add a tristate function to the driver and control it by an additional signal.

    The software handbook also mentions the option to edit internal memory contents at simulation breakpoints.