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Altera_Forum's avatar
Altera_Forum
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16 years ago

Setting output value in waveform file...

Hi, I have a waveform file with some input and outputs.... When I simulate, I get what it's expected... So, there's no problem. But, I would to set some output (at the begining of the wa...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

If you are using VHDL, just for simulation, try this:

signal rx: std_logic_vector(7 downto 0):= "xxxxxxxx"; --Any value

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----

your_output<=rx;

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rx should be a register output.