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Altera_Forum
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9 years ago

Setting bits in a std_logic_vector based on a run time pattern

I am trying to set bits in a std_logic_vector according to a number given from another hit_vector. the hit vector is a combination of three detector hits, and I am trying to decode this back into ...
Altera_Forum's avatar
Altera_Forum
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9 years ago

Why do you have quadrant, sta1/2/3 all set to 0 at the beginning of the process? because of the way VHDL works, this means that whenever you get a falling edge of clk, they will be set to 0, and the code will not synthesise. Remove these assignments and try again.,..