Forum Discussion
JOter
New Contributor
New ContributorSet_output_delay commands does not apply to the output signal
We have a design where we control an external RAM memory. We generate the CLK and control memory signals in a FPGA (Cyclone IV). The CLK signal is generated using a PLL, with 180º phase shift. The ...
KhaiChein_Y_Intel
Regular Contributor
Regular ContributorHi,
The delay is the same becuase the register is located in the I/O. The dalay from the register to the port is the same. Do you see timing violation when you set the output delay value to 12 and higher? If you move this register out of the I/O, you will see some differences in your oscilloscope.
Thanks.
