set_output_delay -min / -max does not have intended effect

Thanks Rysc. I changed the operating conditions to 'fast' and i now have one failed path:

Slack: -0.159

From node: ...dffs[0]

To node: N_SLWR

Launch clock: pll_clk_48

Latch clock: CLK_OUT_48

I assume this is the 1ns hold time that has been eaten up by the faster model.

How is the above best fixed? I believe i have my design optimized for speed per the design assistant's directions.

Edit: I fixed the fast model th violation by Selecting "Standard fit (highest effort)" in the QII Fitter settings. My design now passes both fast and slow timing models.

Thanks again,

/John.