set_output_delay -min / -max does not have intended effect

Also, why are all output timings related to the input clock to the PLL and not to the actual clock the data is related to (in this case the source-synchronous interface)? It seems rather insane, especially in cases where the PLL output clock is not integer multiple of the PLL input clock. It seems useless to me to receive timing information that says that the clock to output delay is 17ns when the clock is not the one i'm interested in looking at.