set_output_delay -min / -max does not have intended effect

Hi Rysc,

I have attached the reports as well as my updated SDC file. I previously had some warnings in the Quartus build log that are now gone. I now get an interesting message in the 'warning' log which seems to indicate that a correct routing delay has been inserted:

Warning: 17 (of 9813) connections in the design require a large routing delay to achieve hold requirements. Please check the circuit's timing constraints and clocking methodology, especially multicycles and gated clocks.

Unfortunately, the DATA_OUT or N_SLWR setup and hold timings have not changed as seen on my Logic Analyzer. I'm using the LAI outputs but i would assume that the timings acquired via LAI should be the same as seen on the output pins?

Thanks,

/John.