set_output_delay -min / -max does not have intended effect

Just looking at the timing constraints, I don't see it as source synchronous, and think it might be set up incorrectly. Your clk_out_48 gets a create_clock assignment, which means a clock comes into it. If this is an output, create a generated_clock assignment on it, and the -source should be the PLL output name that is a generated clock(I'm assuming a PLL is driving this output). That will make a drastic change in your timing results, if that's how your circuit actually works. If everything is going into the output register, there is a fine grained output delay chain in Cyclone II(search for IOE programmable delay in the handbook to see the values), but I think they are too small to meet your delay requirement of padding the data by 5ns. The fitter might move the registers out of the IO cell to meet timing, but that's only once the constraints are correct.