set_output_delay -max -ve?

Regarding the actual meaning of set_input_delay & set_output_delay:

When I first knew about them from AN433, I was totally confused and it didn't make sense at all if I interpreted them as delay to be inserted inside fpga. The name of these commands does convey that message "set input delay, set output delay". Moreover the help menu vindicated that it is delay with respect to clock.

Looking at the equations of both, I came to firm conclusion that they mean something else. My conclusion on set_input_delay was that we are giving info to compiler about data relation to clock at input pins of fpga rather than asking it to insert those delays.

My conclusion on set_output_delay stayed vague for months.

The mystery was solved by looking somewhere else: At Actel SDC documents and I am sure they follow the same standards set by Synopsys.

In Actel document, the definitions are crystal clear:

set_input_delay is indeed about telling the compiler the expected delay of incoming data with respect to incoming clock.

set_output_delay is about asking the compiler to put data before the clock edge by value of delay. Now I understand why max delay = tsu

and min delay = -tH (ignoring trace delays). Thanks to Actel.

With respect to Rysc's explanations, I am afraid it is not right to assume the two parameters of setup relationship and max delay in the way he describes them. setup relationship is used by altera to mean which clock edges are taken as lauch/latch pairs for setup checks.

AN433 clears states and I quote about set_output_delay "It defines the setup relationship with the destination register.

I believe strongly that Altera docs on TimeQuest are a complete mess and making fuss out of trivial differences of actual results from compiler.