Forum Discussion
Occasional Contributorset_max_skew giving path not found warning
Hey,
I have the exact same problem. https://community.intel.com/t5/Intel-Quartus-Prime-Software/Crossing-Clock-Domain-Problems-Timing-Analyser-ignores-set-max/td-p/1308590 .
However it works during the place and route and also the designs output is correct. I can not detect any metastability.Am I right assuming that this error just occurs while using the Timing Analyser and no error is thrown during compilation?
Sadly I also got no answer as do other people with the same question (looking through the forum it gets asked at least once a week I would say).
Best regard
Christian
Super ContributorHi Jaya,
Can you change your constrain as below as see if reflect any changes?
From:
set_clock_groups -asynchronous -group [get_clocks {spi_clk spi_virt_clk}]
To:
set_clock_groups -asynchronous -group [get_clocks {spi_clk}] -group [get_clocks {spi_virt_clk}]
Occasional ContributorHi Syafieq,
I can attempt that. Could you explain why I should put the clk and related virtual clock in two groups? I do expect those clocks to be related and the paths between them to be analyzed. The spi_clk and spi_virt_clk are used to analyze the spi interface and the virtual clock is to constrain the IO of the SPI interface.
