Forum Discussion
Occasional Contributorset_max_skew giving path not found warning
Hey,
I have the exact same problem. https://community.intel.com/t5/Intel-Quartus-Prime-Software/Crossing-Clock-Domain-Problems-Timing-Analyser-ignores-set-max/td-p/1308590 .
However it works during the place and route and also the designs output is correct. I can not detect any metastability.Am I right assuming that this error just occurs while using the Timing Analyser and no error is thrown during compilation?
Sadly I also got no answer as do other people with the same question (looking through the forum it gets asked at least once a week I would say).
Best regard
Christian
Occasional ContributorI have attached the screenshot from the RTL viewer. Both the registers are clocked by asynchronous clocks and I have declared the clocks as asynchronous by using clock groups.
Report max skew summary turns up empty.
I can see the setup/hold details for the individual registers.
