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Again, maybe I'm missing something, but I thought that when I apply the constraint;
set_max_skew -to [get_ports data_out
[*]] 0.1
I'm telling Quartus that when it compiles the design, it should do so in a way that maintains a maximum skew between my data outputs of 100ps. If it fails to meet that criterion, then it gets reported as a timing violation, much the same as a failure to meet tSU/tH. No?
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The target of TQ is to achieve timing closure and that is equivalent to having +ve tSU/tH slack. Once achieved, it doesn't for example even try to optimise tSU/tH balance (except for dc fifos clock crossing paths).
It sees user constraints and things like multicycle are respected as it helps closure.
If you got different skew from your aimed one but timing passed then in effect it says don't worry, it is not needed given your io constraints
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