set_input_delay constraint

It seems that the data delay is too long with the clock and input delay and it works because the delay is in fact not as long as I told Quartus.

I think I that I have to redesign the whole state machine including clocks. After I combined my two FSMs for reading and writing with a FIFO to a loopback the reported FMAX is lower than my clock and output delays of some data pins can not be met.

Before I start I have some questions:

The interface has a maximum tCO of 7 and 8ns (data/flags). And a tCDH (clock to data hold) of 2ns. At the interface clock of 100MHz I only have a data valid window of 5ns around the clock. Currently I have the fpga_clock and the inverted fpga_clock as PCLK and no output registers. Then my setup relationship between launch and latch clock is for outgoing data is 5ns, right? Would it be better to add a register to every signal going to the interface? This way I would have a looser setup relationship?

How can I constrain that I only have a data valid window of 5ns?

If I have a clk100 generating the data and control signals for writing to the interface and a clk100_shifted clock to meet setup times on the interface side and another phase shifted clock for clocking in the data read from the interface. Couldn't I get problems with setup times between the clk100 and the clock latching the the FLAGS/data from the interface because I need to read the signals in the clk100 domain.

Thank you for your detailed answers!