set_input_delay constraint

I assume tCO of 6~8 ns is from external chip data sheet and must be relative to the launch edge at external chip clock pin. What you are telling Timequest is that the 6~8 ns is relative to fpga out_clk. This possibly is the source of conflict.

The FlagD is sampled by an internal fpga clock and timequest relates that to fpga out_clk, hence it sees data arriving (may be) too early if for example the latch clock at FlagD register is delayed inside fpga by say 4ns relative to clk_out.

so you need either to modify tCO relative to fpga clk_out or create virtual clock delayed from clk_out then use it as reference for set_input_delay.