set_input_delay constraint

Thank you for the reply! Yes, you're right. The tco_max of 8ns is correct and tco_min with 0 is wrong. I set the tco_min now to 6ns and added the clock delays to the min and max values. But the timing still fails.

Here are my settings:

set tbd_data_min  0.65
set tbd_data_max  1.26
set tbd_clk_min   0.72
set tbd_clk_max   1.15
set tco_fx3_min   6
set tco_fx3_max   8 
set in_max_delay 
set in_min_delay 
set_input_delay -clock {out_clk} -max $in_max_delay 
set_input_delay -clock {out_clk} -min $in_min_delay 
set_multicycle_path -setup -from  2

With these settings the FLAG is sampled correctly in the FPGA but the timing report says the timing requirements aren't met. The data path from the FLAGD pin to the register is reported to be 2.383ns. And the timing report shows a slack of -1.024. The interface is the synchronous slave fifo of an FX3. The specs are in http://www.cypress.com/file/136056/download (http://www.cypress.com/file/136056/download) starting on page 6.

Are these values already relative to my PCLK clock output pin? I also added "-reference_pin [get_ports PCLK]" but got the warning "Reference pin PCLK is invalid. It is not clocked by the clock specified in set_input_delay/set_output_delay's -clock option".

Do you have an idea why it still fails?