Honored Contributor
Honored ContributorI'm just looking at the FLAGD input. At 100MHz, with a launch on falling edge and multicycle setup of 2, you should have a setup relationship of 15ns and hold relationship of 5ns. This makes sense as the difference is 10ns, which is your data rate. So right off the bat, your external max is 9.26ns and your min is 0.65ns, for a difference of 8.61ns. So 8.61ns of your 10ns window is already chewed up before the FPGA delays are even taken into account.
I can say right now that the max/min spread in the FPGA will be greater than 1.39ns(I'm 98% sure). I just don't think this interface can work with those specs. The first thing I would check is the tco_fx3_min of 0ns. If the other device has a PLL it's possible to get a Tco close to 0, but then the max wouldn't be 8ns. I'm guessing it doesn't have a PLL, the 8ns max is correct, and the 0ns min is not real. I'd be curious what it is if you measure it. But when an external device chews up 8ns of the data window, it really can't run at 100MHz. (If the min increased to 4ns, for example, it still might be tough to meet timing, but closer to possible. You might have to do some tricks like have the latch and launch clocks on different outputs of the PLL and phase shift one or the other. Hard to say without knowing the specs and having something to compile). I did that analysis quickly, so let me know if I missed anything. Good luck.
