Set GPIO pins with multiple voltage levels

Not strictly true. Using the tri-state output capability, one could transmit a HIGH level (ie, ~3.3V), a LOW level (~0.0V), and a MID level (~1.65V) by having equal value resistive pullup/pulldowns attached to the signal net to set the mid level (ie, having a 3.3K pullup and 3.3K pulldown on the signal line). So one could theoretically have tri-level signaling with a standard FPGA output, at close to the maximum data rate (subject to the RC time constant of the net).

Detecting the tri-levels at an FPGA input however is another matter. No FPGA inputs are setup for other than bi-level signal detection.

If your data rate is very slow, you could use PWM encoding on a signal net, and RC filter it to approach what an digital to analog converter would produce. Generating 16 to up to 256 levels should be possible, but the data rate would necessarily have to be very low (1KHz or less). Noise budget would need to be carefully considered, as 256 levels at 3.3V is about 12mV per level. Detection would again be an issue, and would require an A/D and careful circuit design.

So it can be done if you can live with the significant limitations.