set false path if over some logic levels

There isn't any easy command that dumps the levels of logic. You can get timing reports and go through each one and get that info, but it would be very time consuming, and would require a complex flow(synthesize, do timing analysis and find all the long paths, create an .sdc, then run the fitter...)

FYI, levels of logic is not a good indicator in FPGA's because they can vary so much. For example, I see paths with 16-32 levels of logic that run very fast, but that's because they're in a carry chain. Conversly, I see single levels of logic that are a memory with no output registers, and hence a large access time that would probably equal a few levels of logic in LUTs. On top of that, there's a lot of variance. There are some paths through a LUT that are extremely fast, and some that are very slow. Adding it all up, it makes "levels of logic" a measure that isn't overly useful. (When looking at a path, one can quickly see these things and understand them, so we still report the levels of logic, I'm just saying it hasn't been pursued as a means for identifying things.)

Can you do the opposite and just look for large failures? That comes out of report_timing much easier, and I assume is a similar issue?