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Altera_Forum's avatar
Altera_Forum
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16 years ago

Set constraint for timequest

hi. i just start to use timequest. some simple question wondering me and needs confirmation. 1. If use the clock enable method as frequency divider, is necessary to set constraint? 2. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Thanks for details explanation. I learn a lot..

Some fact confuse me:

"the P&R tools will attempt to optimize your design so that paths between FF's are minimized to meet 200MHz timing" causing area bigger.

From my point of view, if paths between FF's are minimized to meet 200MHz timing, then the area should be getting smaller instead of bigger due to the FF related have to placed closer, shortening the length of wire.

Pls correct me if i am wrong..

Question:

In the case of setting multicycle for the path related, then it would be a lot. It is because my whole project is done like this(using clock enable). So, any efficient way like to set multicycle for whole design except the frequency divider?

thanks