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However, this will result in a over-constrained circuit: TQ will ignore the clock enable and analyze the circuit as if the clock is always enabled.
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May you explain? i have no idea why it cause this.
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If the circuit can meet your required timmings in thisway and you're happy with the area it's taking, then fine.
If not, you'll have to relax the timing constraints for the clock-enable driven circuit by setting mutli-cycle constraints.
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FYI, there is a lot of articles advice to use the clock enable method instead of frequency divider to avoid clock skew. Besides, will this method caused multi-cycle? May i know the reason?
2. No.
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Not familiar with the NCO, but are you using any of it's outputs as a clock signal?
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Nope. The are a lot of internal pins that i can't access causing a lot of warning.
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