set_clock_groups vs. set_max_delay/set_min_delay

We are encountering issues in a design where gray counters are used on a big ArriaV device which could be related to this. Currently the constraints are simply set_clock_groups constraints so in theory the skew between the different bits could be too large.

How can I check this as report_skew doesn't find any paths because of the set_clock_groups constraint?

Is there now a way to constrain busses (such as gray counters) for a max delay without 'breaking' the clock_groups constraint (as set_max_skew cannot be used with set_clock_groups)? It will be quite cumbersome if we need to constrain every path which crosses clock domains. An option could eventually be added which makes set_max_skew as a higher priority than clock_groups_constraint...