Honored Contributor
Honored ContributorThe path perchrc describes is register to register, so there's no combinatorial logic. The assumption is that there should never be 8ns of skew between multiple bits, and I would say that's a pretty safe assumption. You can usually go across chip and meet 8ns, and the fitter is going to put these paths pretty close together just to reduce routing(even if it doesn't care about timing). That all being said, I understand that without a constraint, how do you really know for sure.
(Another option is to run report_skew on the paths in question on the back-end. You would have to load an .sdc that doesn't do the set_clock_groups, but it would be a pretty easy test.)
