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Sorry for that, you are right! the period was intended to be 0.1ms NOT 0.2 so I reduce the divisor to 2499 and its already working. What I don't really understand is why I have to divide the divider by half, for example if I have a 50MHz clock and it needs to be down to 10KHz, the divider is 5000, right. I understand the code takes a count every rising edge, but if I need 5000 cycles of 20ns (50MHz) to get a 0.1ms period signal why do I need to specify the divider as 2500 if in 5000 cycles, there are 5000 rising edges!
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count1 is meant to divide the 50MHz clock into 10KHz clkout so you need to divide by 5000 (mathematically).
At implementation using counter you either need 5000/2 counter since at each 2500 count you invert clkout (2500 cycles to invert clkout from 0 to 1 and 2500 cycles to invert from 1 to 0) or use 5000 counting and invert at 2500 and 5000
count2 counts 200 clock
edges.so count2 is correct as you are just counting edges of the 10KHz clkout
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