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Thanks FvM,
I understand that always@(posedge clk) is equivalent to clocked process with rising_edge(clk) in VHDL, that's why I think a registered output of FSM can be described directly by using
always@(posedge clk) (namely 'TestSignal' is supposed to rise in the following clock cycle if the state transits to st5 in the current clock cycle, not necessarily at clock edge), however in my experiment the output came out within the same clock cycle as the one where the state transits to st5. This is what confuses me.
I'v no idea what goes wrong, now in order to have a registered output, I need to raise a flag (combinatorial signal) when the state transit to st5, then use
always@(posedge clk) block to trigger the output TestSignal when the flag rises. Why can't I use always@(posedge clk) block to monitor the state directly?
Thanks
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If your st5 indeed transitions at current clock edge then it is sampled on next clock edge to be known and so raise TestSignal.
If you are getting both at same edge then you are doing something wrong. For example your state transitions on a different clock. You better show more of your code.
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